1. Field of the Invention
The present invention relates generally to integrated circuit devices and more specifically to integrated circuit memory devices with redundant memory cells for replacing defective memory cells.
2. Background of the Invention
Integrated circuit memory devices comprise arrays of memory cells arranged in rows and columns. Generally, memory cells in each row of the array are tied to a common wordline and memory cells in each column of the array are tied to a common bitline. The bitlines are used to write and read data into the memory cells and the wordlines are used to select which memory cells along a given bitline the data is written into.
When a memory cell fails, the entire bitline that the failing cell is attached is no longer useable. In order to increase yield and reduce cost, memory devices are often provided with redundant bitlines. A test is performed and defective memory cells and the bitlines they are attached to determined. Then the failing bitline is “disconnected” from the array and replaced with a non-defective spare or redundant bitline. This replacement requires that data originally intended for the failing bitline, be “steered” to the replacement bitline.
While many schemes have been developed for steering data to redundant bitlines, they all share the same problem in that they leave a data line feeding the failing bitline floating. This problem is of particular concern in certain memory devices, for example, such as content addressable memories (CAMs) where floating data lines can lead to erroneous address information being passed out of the CAM. Therefore, there is a need for a technique of replacing bitlines that overcomes the potential problem caused by floating data lines.